1. Field of the Invention
The invention relates generally to the fabrication of semiconductor devices and to polishing and planarizing of substrates.
2. Background of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology has placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias, contacts, lines, and other interconnects. Reliable formation of these interconnects is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
In order to further improve the current density of semiconductor devices on integrated circuits, it has become necessary to use conductive materials having low resistivity for conductors and dielectric materials having a low dielectric constant (low k, defined herein as having dielectric constants, k, less than about 4) as insulating layers to reduce the capacitive coupling between adjacent interconnects. Increased capacitative coupling between layers can detrimentally affect the operation of semiconductor devices.
As such, low resistivity materials, such as copper, and low k dielectric materials, such as carbon doped silicon oxides or other organic-inorganic dielectric materials, are being used to form semiconductor features. For example, copper is utilized in dual damascene structures where vertical and horizontal interconnects of a dual damascene feature definition are etched out of the low k material. A diffusion barrier material and then are deposited therein, and the upper surface of the substrate is polished to form the dual damascene feature. Polishing removes both the copper and the low k dielectric material to produce a planarized surface suitable for further processing of the substrate. As a result, chemical mechanical polishing is being used to provide planarization of the substrate, and new processes and compositions are being developed to improve removal of substrate materials, such as the low k dielectric materials.
Conventionally, in polishing copper features, such as in a dual damascene structure, the copper material is polished to the barrier layer, and then the barrier layer is polished to the underlying dielectric layer to form the dual damascene feature. One challenge which is presented in polishing dielectric materials is that dielectric materials are often removed at different rates in comparison to the copper material and barrier material with different compositions and in different applications. For example, in a selective polishing process during barrier removal for copper damascene structures, a high barrier removal rate and low dielectric removal rate is desired to minimize total metal loss. In a non-selective process, a high removal rate of both the barrier layer and the low k dielectric material is desired to achieve good planarization. In other applications, such as where the logic and memory chips are integrated, a much higher removal rate of the low k dielectric films in comparison to the surrounding material is needed. Conventional compositions typically remove dielectric materials at relatively low rates compared to surrounding materials, such as conductive materials or metals.
Therefore, there exists a need for a method and related polishing composition which facilitates the removal of dielectric materials at desired rates for different manufacturing applications.
The invention generally provides a method and composition for planarizing a substrate surface with controllable removal rates of low k dielectric materials. In one aspect, the invention provides a composition for planarizing a substrate, the composition comprising one or more chelating agents, one or more oxidizers, one or more corrosion inhibitors, a polar solvent, and deionized water. The composition may further include one or more surfactants, one or more agents to adjust the pH of the composition. The CMP composition may also include an abrasive particle concentration of about 10 wt. % or less.
In another aspect, the invention provides a method for removing at least a portion of a material from a substrate surface, the method comprising planarizing the substrate surface using a composition including a polar solvent. The composition further comprises one or more surfactants, one or more chelating agents, one or more oxidizers, one or more corrosion inhibitors, deionized water, and may optionally include one or more agents to adjust the pH of the composition and/or abrasive particles.
Another aspect of the invention provides a method for processing a substrate, comprising forming an aperture in a low k dielectric layer disposed on the surface of a substrate, depositing a barrier layer on the dielectric layer and in the aperture, depositing a metal layer on the barrier layer to fill the aperture, and planarizing the substrate using a composition including, a polar solvent, one or more chelating agents, one or more oxidizers, one or more corrosion inhibitors, and deionized water. The method may further include a composition further containing one or more surfactants, one or more agents to adjust the pH of the composition or abrasive particles.